Integrated bias resistors for micro-logic circuitry



Dec. 10, 1968 R. E. BOHN ETAL 3,416,049

INTEGRATED BIAS RESISTORS FOR MICRO-LOGIC CIRCUITRY Original Filed May 17, 1963 3 Sheets-Sheet 1 OUTPUT OUTPUT RICHARD H BOHN- and RICHARD C. SIRRINE INVESTORS.

AGENT.

Dec. 10, 1968 R. E. BOHN ETAL 3,416,049

INTEGRATED BIAS RESISTORS FOR MICRO-LOGIC CIRCUITRY Original Filed May 17, 1963 5 Sheets-Sheet 2 OUTPUT OUTPUT CP SET RESET CP -V IFIG.3

RICHARD E. BOHN and RICHARD C. SIRRINE,

INVENTORS.

BY 5*; m M

AGENT.

Dec. 10, 1968 Original F'iled May 1'7, 1963 \FIG.4

IFIG.6

R. E. BOHN ET AL INTEGRATED BIAS RESISTORS FOR MICRO-LOGIC CIRCUITRY 3 Sheets-Sheet 5 3 P N+ 33 P+ N P+ so 31 32 P7! [F IG. 5 RICHARD E. BOHN and RICHARD c. SIRRINE,

INVENTORS.

AGENT.

United States Patent 3,416,049 INTEGRATED BIAS RESISTORS FOR MICRO-LOGIC CIRCUITRY Richard E. Bohn, North Reading, and Richard C. Sirrine, Winchester, Mass, assignors to Sylvania Electric Products Inc., a corporation of Delaware Original application May 17, 1963, Ser. No. 281,183, now Patent No. 3,229,119, dated Jan. 11, 1966. Divided and this application June 30, 1965, Ser. No. 468,415

2 Claims. (Cl. 317-235) ABSTRACT OF THE DISCLOSURE Transistor circuit element of the double-diffused type having an elongated base region. A first ohmic contact is made to the emitter region, a second ohmic contact is made to the base region closely adjacent the base-emitter junction, and a third ohmic contact is made to both the collector and base regions at a distance from the second contact. The portion of the base region between the second and third contacts serves as a resistance between the collector and base of the transistor.

This application is a division of application S.N. 281,- 183 filed May 17, 1963, now Patent No. 3,229,119.

This invention relates to logic circuits employing transistors. More particularly, it is concerned with digital information handling circuits in which transistors are employed for switching, amplifying, inverting, and output level voltage setting.

The operating requirements for circuits employed in performing logic functions are becoming more stringent as the art of digital computers and data processing equipment advances. In particular, the time required for a circuit to perform a logic operation is a limiting factor on the data handling capability of computing apparatus. Problems are also encountered in providing circuits which are immune to noise, whether generated within or externally of the circuit. Logic circuits may also be restricted in their usefulness because of limited fan-out. Fan-out is a measure of the number of succeeding logic circuits which can be operated with parallel input connections to the output connection of the circuit.

Size is also a significant consideration in the high speed data processing art. Logic circuits have been designed for fabrication within a single chip or die of semiconductor material. With these so-called integrated circuits the size of a complete logic circuit is reduced to that of a single standard electrical component. However, integrated logic circuits have certain problems in addition to those common to logic circuits in general. The ability to dissipate power is limited, and this situation may result in restricting the circuit to low fan-out. Since all of the components are located on a single small piece of semiconductor material there are problems of interaction between the individual components. In addition, the available electrical current may be limited and certain of the components may be deprived of the current necessary for proper operation.

It is an object of the present invention, therefore, to provide improved logic circuits.

It is a more specific object of the invention to provide logic circuits which have improved operating characteristics and which are amenable to fabrication as integrated circuits.

It is also an object of the invention to provide an integrated logic circuit incorporating an element which combines the electrical functions of more than one type of electrical component.

Briefly, logic circuits in accordance with the foregoing 3,416,049 Patented Dec. 10, 1968 objects of the invention include an input circuit means wh1ch s adapted to produce a signal in response to a predetermined signal condition at its input. A first transistor circuit means connected to the input circuit means produces signals at first and second output connections in response to a signal from the input circuit means. A second transistor circuit means is responsive to a signal at the first output connection to change the voltage level at an output terminal from a first predetermined voltage output level to a second predetermined voltage level. The second transistor circuit means is also adapted to restore the voltage level at the output terminal to the first predetermined voltage level in response to termination of the signals at the first and second output connections.

It is a feature of the invention to provide an integrated circuit element in the second transistor circuit means which combines the functions of a transistor and a resistor with the resistor connected between the base and the collector of the transistor. The element also produces premature saturation effects in the transistor upon the existence of short circuit conditions in the collector-emitter circuit.

Additional objects, features, and advantages of logic circuits according to the invention Will be apparent from the following detailed discussion and the accompanying drawings wherein:

FIG. 1 is a schematic diagram of a dual NAND logic circuit gate according to the invention,

FIG. 2 is a schematic diagram of a NAND-OR logic circuit according to the invention,

FIG. 3 is a schematic diagram of a set-reset flip-flop circuit according to the invention,

FIG. 4 is a plan view of the dual NAND logic circuit shown schematically in FIG. 1 embodied as an inte grated circuit in a die of semiconductor material,

FIG. 5 is an elevational View in cross section of a portion of the semiconductor die ofFIG. 4 taken along lines 5-5 of FIG. 4 showing an integrated circuit element which combines the functions of a transistor and resistor in a single element and FIG. 6 is a circuit diagram of the equivalent circuit of the portion of the integrated circuit of FIG. 4 shown in the cross sectional view of FIG. 5.

FIG. 1 is a schematic circuit diagram of a dual NAND logic circuit gate according to the invention. The circuit network as shown includes two identical circuits 10 and 11 each of which is an independent NAND logic circuit.

The first NAND circuit 10 may be considered as being off when no input signals are being applied at the input terminals A A and A The voltage at the terminals is at a low level and in logic terms may be called a false voltage. Under these conditions the voltage at the output terminal A is at a high level which may be termed a true voltage. Only during the concurrent occurrence of true voltage input signals at all three input terminals A A and A does the circuit turn on and produce a low level false voltage at the output terminal A. When a false voltage exists at one or more of the input terminals A A and A the circuit is off and a true voltage is produced at the output terminal A.

The low level or false voltages and the high level or true voltages produced at the output terminal are of the same value as those applied at the input terminals. Therefore, logic circuits according to the invention can be connected together serially and in parallel in any desired combination in order to process digital information.

The NAND logic circuit 10 of FIG. 1 includes an input circuit section which performs an AND logic function. In the particular circuit shown an NPN input transistor T has its base electrode connected through a resistance R to a source of positive voltage V The input to the transistor includes three emitter electrodes each of which is connected to an input terminal A A and A The collector electrode of the input transistor T provides the output connection from the input section.

The logic function of inverting a signal from the input section in addition to the functions of amplifying and output voltage level setting are performed by a transistorized circuit section. A first NPN transistor T in this section has its base electrode connected to the output connection from the input section. Its collector electrode is connected through a collector resistance R to the positive voltage supply V The emitter electrode is connected through a pull-down resistance R to a source of negative voltage V An NPN output transistor T has its base electrode connected to the emitter electrode of the first transistor T its emitter electrode connected to ground, and its collector electrode connected to the output terminal A of the circuit.

The amplifying and inverting section also includes an NPN voltage setting transistor T which has its base electrode connected to the collector of transistor T and its collector electrode connected to the positive voltage source V The emitter electrode of the voltage setting transistor is connected through a diode D to the output terminal A. The diode is connected for forward conduction from the emitter electrode to the output terminal A.

The NAND logic circuit 10 of FIG. 1 operates in the following manner. When the input terminals A A and A are all at the low voltage false level the circuit is off and a high voltage true level is produced at the output terminal A. The low voltage level at an input terminal may be caused by a low impedance between the terminal and ground. In this situation current flow from the supply V through the input resistance R the baseemitter diode of the transistor T and the low impedance connected to the input terminal produces a low voltage at the terminal. The low impedance between the input terminal and ground may be caused, for example, by an on condition in a preceeding logic circuit according to the invention to which the input terminal is connected, as will be apparent from the explanation hereinafter.

With the emitters of the input transistor T at a low voltage level, current from the supply V flows through the input resistance R and the base-emitter diodes of the transistor. The greatest voltage drop occurs across the resistance R causing the voltage at the base of the input transistor T to be relatively low. Conduction in the collector circuit is thus slight and the voltage at the collector of the transistor is low.

The first transistor T of the inverting and amplifying section of the circuit is connected in series with collector resistance R and pull-down resistance R between the positive voltage supply V and the negative voltage supply V The magnitude of the voltage of the negative source V is slightly less than that of the positive source V and the resistance R is approximately five times the resistance of the resistance R This biasing arrangement is such that when the no signal low voltage from the collector of the input transistor T is applied at the base of the transistor T a small current flows through the transistor and the two series connected resistances R and R A fairly high voltage is thus established at the collector of transistor T and a fairly low voltage, slightly below ground, at the emitter.

Since the voltage produced at the emitter of the transistor T is low, the output transistor T is biased in the non-conducting condition. In this condition the transistor presents a high impedance between the output terminal A and ground.

The voltage at the collector of the transistor T is applied to the base of the voltage setting transistor T Under normal off conditions of the circuit the small leakage current of the output transistor T flows through the voltage setting transistor T although both transistors can be considered as being substantially non-conductive. The voltage drop across the forward resistance of the base-emitter diode of the transistor T and that of the series connected diode D establishes the voltage level at the output terminal A.

As is well understood in the art of semiconductor logic circuits, when the voltage signal level at any one of the input terminals A A or A is raised to the high voltage true level as by virtue of its being connected to the output terminal of a logic circuit which is turned otf, no change occurs at the collector electrode of the input transistor T Current flow through the base-emitter diode to the input terminal stops, since the diode is reverse biased. However, current continues to flow through the input resistance R and through the other base-emitter diodes of the transistor T Thus, the voltage at the base electrode of the input transistor T is not changed, and the logic circuit remains off. This situation continues to exist regardless of the number of input terminals so long as any one of them is biased at the low voltage false level.

When the voltage levels at A A and A are at the high voltage true level concurrently, current from the supply V can no longer flow in the same manner because all the base-emitter diodes of the transistor T are reverse biased. As the flow of current is reduced the voltage at the base of the input transistor T rises thereby causing conduction through the transistor and increasing the voltage on the collector. This action at the base electrode of the transistor T causes greatly increased conduction through that transistor.

The increased current flow through the transistor T and its series connected resistances R and R lowers the voltage at the collector electrode and raises the voltage at the emitter electrode. The output transistor T is thereby biased to conduction providing a low impedance path between the output terminal A and ground and establishing a low voltage false level at the output terminal.

The voltage at the base electrode of the voltage setting transistor T is such as to insure that the transistor remains in a non-conducting condition maintaining the output terminal A at a low voltage signal level.

Upon termination of the high voltage level signal at one or more of the input terminals A A or A a baseemitter diode of the input transistor T becomes forward biased permitting current to flow through the input resistance R The increased 'voltage drop across the resistance R lowers the potential at the base of the input transistor T thereby reducing conduction in the collector circuit and the potential at the collector. This condition biases the transistor T so that only slight conduction occurs through the transistor and series connected resistances R and R The voltage at the collector of the transistor T is thereby increased and that at the emitter is reduced.

The reduced voltage at the emitter electrode of transistor T biases the base of the output transistor T so as to render that transistor non-conducting. The output transistor T thus presents a high impedance between the output terminal A and ground. The increased voltage applied at the base of the voltage setting transistor T together with the low voltage level existing at the output terminal A causes that transistor to conduct. The transistor conducts heavily until the voltage at the output terminal A is restored to the level established by the voltage at the transistor base less the forward biasing voltage drop across the base-emitter diode of the transistor and the diode D The voltage at the output terminal A fails to revert to the high level immediately upon termination of current fiow through the output transistor T because of various capacitance effects on the output terminal A and its external connections. In order for the voltage at the outall three input terminals put terminal A to rise, this load capacitance-must be charged. The heavy flow of current from the supply V through the voltage setting transistor T charges the load capacitance very rapidly. When the output terminal A reaches the upper voltage true level as established by the voltage at the base of the voltage setting transistor T the transistor no longer conducts and the logic circuit is off.

The second logic circuit 11 of the dual NAND gate operates in exactly the same manner as does the first circuit providing a NAND logic function having three input terminals B B and B and an output terminal B.

FIG. 2 is a schematic circuit diagram of a NAND-OR circuit gate in which a low voltage false level is produced at the output terminal C when there is a coincidence of high voltage level input signals at input terrninals C C and C or when there is a coincidence of high voltage level input signals at input terminals C C and C When neither of these conditions exists at the input, a high voltage true level is produced at the output terminal C.

The input terminals C C and C are connected to the three emitter electrodes of a first input transistor T This transistor is connected in a manner similar to the input transistor of FIG. 1. Its base electrode is connected through a first input resistance R to the positive voltage source V and its collector electrode is connected directly to the base of a first transistor T in the amplifying and inverting section of the circuit. The input terminals C C and C are similarly connected to the emitter electrodes of a second input transistor T having its base electrode connected through a second input resistance R to the voltage source V and its collector electrode connected to the base of a second transistor T in the amplifying and inverting section.

The emitters and the collectors of the first two transistors T 03 and T in the amplifying and inverting section are connected directly together. The common collector connection is connected through the collector resistance R to the positive voltage source V The common emitter connection is connected through a base pull-down resistance R to a source of negative voltage V An output transistor T is connected in a manner similar to the output transistor in the circuit of FIG. 1. The base is connected to the common emitter connection of transistors T and T 4, the emitter is connected directly to ground, and the collector is connected directly to the output terminal C.

A voltage setting transistor T is also connected in the circuit similarly to the voltage setting transistor of FIG. 1. The base is connected to the common collector connection of the two transistors T and T r, and the collector is connected directly to the positive voltage source V The emitter is connected through a diode D to the output terminal C.

A coincidence of high voltage true signals at the input terminals C C and C causes increased conduction through the first transistor T of the amplifying and inverting section in accordance with the explanation of the operation of the circuit of FIG. 1. The signal produced at the emitter of transistor Tcg causes the output transistor T to conduct thereby reducing the voltage at the output terminal C to the low false level.

Similarly a coincidence of true input signals at the input terminals C C and C causes increased conduction through transistor T This condition affects the base of the output transistor T switching that transistor to a. high conduction condition and reducing the voltage at the output terminal C to the low false level. Thus, an increased conduction condition in either transitor T or T causes the logic circuit to turn on and a low voltage false level to be produced at the output terminal C.

When a change occurs in the input terminals so that signals input transistors T and T voltage signal levels at the from one or both of the become terminated and no signals are transmitted to transistors T and T conduction through transistors T and T is slight. The resulting conditions at the common emitter connection and at the common collector connection cause the output transistor T to become nonconductive and the voltage setting transistor T to become conductive. Current flows through the voltage setting transistor charging the load capacitance until the output terminal C is restored to the high voltage true level. The manner of operation of the circuit to obtain rapid turning off is the same as that previously described in the discussion of the logic circuit of FIG. 11.

A set-reset flip-flop network 20 is illustrated in the circuit diagram of FIG. 3. The network includes two crosscoupled NAND circuits 21 and 22 according to the invention together with pulse-level input gates. When the network is functioning, one of the NAND circuits is on while the other is off. The operating states of the circuits are reversed by a suitable combination of input signal conditions serving to turn the on circuit off.

The first NAND logic circuit 21 is the same as either of the NAND circuits of FIG. 1. It includes a three input AND section having a three emitter transistor T with its base connected through a resistance R to a positive voltage source V Input connections are made to the emitters of the transistor and the output is taken from the collector.

The output for the AND section is applied to the base of a first transistor T in the amplifying and inverting section of the circuit. The collector of transistor T is connected through a resistance R to the positive voltage source V and its emitter is connected through a resistance R to a negative voltage source V An output transistor T has its base connected to the emitter of transistor T its emitter connected to ground, and its collector connected to an output terminal D. A voltage setting transistor T has its base connected to the collector of transistor T its collector connected to the positive voltage source V and its emitter connected through a diode D to the output terminal D.

A pulse-level input gate is connected to one of the emitters of the AND section transistor T The gate includes an input gate transistor T having its collector connected to the emitter of transistor T and its base connected through a resistance R to ground. The emitter of the input gate transistor T is connected to a set terminal, and the base is connected through a capacitance C to a first clock pulse terminal CP The second NAND logic circuit 22 is the same as the first circuit 21. A three emitter AND section transistor T is connected to an amplifying and inverting section including transistor T an output transistor T and a voltage setting transistor T The transistors are suitably connected to each other and to resistances and voltage sources to provide the proper voltage level at the output terminal E as explained previously.

A pulse-level input gate is connected to one of the emitters of the AND section transistor T of the second NAND logic circuit. The collector of the input gate transistor T is connected to the one emitter of transistor T and its base is connected through a resistance R to ground. The emitter of transistor T is connected to a rese terminal and the base is connected through a capacitance C to a second clock pulse terminal CP The inputs and outputs of the two NAND logic circuits are cross-coupled by a connection from the output terminal D of the first circuit to one of the emitters of the AND section transistor T of the second circuit and by a connection from the output terminal E of the second circuit to one of the emitters of the AND section transistor T of the first circuit. The third emitter of the AND section transistor T of the first circuit is connected to a DC set terminal and the third emitter of the corresponding transistor T in the second circuit is connected to a DC reset terminal.

In order to explain the operation of the flip-flop network 20, let it e assumed that the first NAND logic circuit 20 is on and the second NAND logic circuit 22 is off. In order for this condition to exist, high voltage level signals must be present at all three emitters of the AND section transistor T The DC set and DC reset terminals are biased at the high voltage level by a continuous DC bias which is altered only to preset the conditions of the network circuits prior to digital operation. Another emitter of transistor T is connected to the output terminal E of the second NAND logic circuit, and since the second circuit is off a high voltage level signal is present at the emitter.

The third emitter of the AND section transistor T is connected to the input gate transistor T There are two input connections to the input gate transistor; the set terminal and the first clock pulse terminal CP The voltage level applied at the set terminal is either the low voltage false level or the high voltage true level. The clock pulse terminal CP is normally biased at a low level near ground, and positive clock pulses are periodically applied to the terminal. During the time interval between clockpulses, the input gate transistor T remains nonconductive regardless of whether the voltage level at the set terminal is high or low. Thus, the input gate transistor T is normally non-conductive and a high voltage level is established at the third emitter of the AND section transistor T In normal operation the flip-flop network is triggered to turn the first NAND logic circuit 21 off and the second logic circuit 22 on by the arrival of a positive clock pulse at the clock pulse terminal CP while a low voltage level signal is being applied at the set terminal. The rising Waveform of the clock pulse is differentiated by the capacitance C and resistance R combination to provide a positive signal at the base of the input gate transistor T If a high voltage level signal is being applied at the set terminal, the signal at the transistor base has no effect and the transistor remains non-conductive. However, if a low voltage signal is being applied at the set terminal, the signal at the base of the input transistor T biases that transistor to conduction.

Momentary conduction through the input gate transistor T caused by a low voltage signal at the set terminal during the occurrence of a positive clock pulse at the clock pulse terminal CP causes a momentary drop in the voltage level at the emitter of the AND section transistor T to which the collector of transistor T is connected. As previously explained in describing NAND logic circuits according to the invention, this condition causes the first NAND logic circuit 21 to turn off. The voltage at the output terminal B is thereby raised to the high voltage level.

In the second NAND logic circuit 22 the DC reset terminal is held at the high voltage level as explained previously and since the pulse-level input gate is not conducting, the emitter of the AND section transistor T connected to the input gate transistor T is at the high voltage level. Therefore, when a high voltage level is established at the third emitter of the AND section transistor T by the connection to the output terminal D, the second NAND logic circuit 22 is turned on. The voltage at the output terminal E is thereby reduced to the low voltage level. This voltage level is applied to an emitter of the AND section transistor T of the first logic circuit 21, thus maintaining that circuit off after the clock pulse at the clock pulse terminal CP has terminated and the input gate transistor has returned to the nonconducting condition.

The operating states of the two NAND logic circuits may be reversed again by a positive going clock pulse arriving at the second clock pulse terminal CP while the reset terminal is being held at the low voltage level. Current flow through the input gate transistor T lowers the voltage on the emitter of the AND section transistor T causing the second logic circuit to turn off, and the connection between the output terminal E and the emitter of the AND section transistor T causes the first NAND logic circuit to turn on.

The dual NAND circuit shown schematically in FIG. 1 is illustrated in the form of an integrated circuit in the plan view of FIG. 4. An elevational view in cross section of a portion of the die 30 of semiconductor material in which the circuit elements are fabricated is shown in FIG. 5. For ease in understanding, the reference characters employed in FIG. 1 are used where applicable in FIG. 4.

As can best be seen from the cross sectional view of FIG. 5 the circuitry is fabricated by epitaxially growing layers of semiconductor material on a substrate and diffusing conductivity type imparting materials into the epitaxial layers. In actual practice hundreds of integrated circuits are fabricated simultaneously on a relatively large slice of semiconductor material. However, for purposes of illustration only a single integrated circuit formed in a small portion of such a slice is shown in FIGS. 4 and 5. The substrate of semiconductor material is a body 30 of single crystal silicon of high resitivity P-type conductivity. A thin layer 31 of low resistivity N-type silicon is grown on the substrate by known epitaxial techniques. Another layer 32 of N-type silicon having higher resistivity is then grown on the first epitaxial layer.

The various circuit elements are then fabricated by a series of steps in which conductivity type imparting materials are selectively diffused into regions of the silicon die. Known techniques of coating the surface of the die with a protective non-conductive oxide layer, masking with a photo-resistant material, and etching to provide openings in the oxide coating through which a conductivity type imparting material may be diffused are utilized prior to each diffusion step to delineate the regions into which the conductivity type imparting material is to be diffused. A P-type conductivity imparting material is first diffused into the appropriate regions of the semiconductor die to provide high conductivity P-type isolating regions 33 for isolating the various electrical elements from each other. Theu, a P-type conductivity imparting material is difilused into regions 34 of the N-type epitaxial layer to provide the base regions for the transistors, the resistance components, and also the anode regions of the diodes. Finally, the emitter regions of the transistors are produced by the diffusion of an N-type conductivity imparting material into regions 35 of the base regions 34. The boundaries, or junctions, of each region of a single conductivity type are indicated by relatively heavy lines in FIG. 4.

Following the diffusion steps, the protective oxide coating 40 is reconstituted, and openings are etched in the coating over the areas on the surface of the die at which electrical connections are to be made to the underlying semiconductor material. The entire surface of the die is then coated with an adherent layer of conductive material, as by vapor deposition of aluminum. Portions of the aluminum layer are then removed by appropriate masking and etching steps to leave a pattern of electrical connections 45 to the circuit elements. The edges of the electrical connections are indicated by relatively thin lines in FIG. 4. The areas at which the electrical connections make contact to electrical elements at openings in the oxide coating are designated by stippling in FIG. 4. Terminals to which the external connections of the circuit are to be made are provided by large areas 46 of the aluminum layer located near the edges of the die. The completed integrated circuit as illustrated in FIG. 4 may be placed in any suitable enclosure having leads to which the terminal areas 46 may be connected.

In the version of the integrated circuit illustrated in FIG. 4 the diodes, four of the resistances, and six of the transistors are generally in accord with known structures of components formed by diffusion of conductivity type imparting materials into semiconductor material. Each of the voltage setting transistors T and T and its associated resistance R and R however, as shown in FIGS. 4 and 5 are fabricated as a single element. Although the NAND logic circuit illustrated schematically in FIG. 1 may be constructed with discrete electrical components or as an integrated circuit in which each electrical function is performed by a separate element, certain advantages are obtained by combining the voltage setting transistor with the associated resistance in a single element.

The P-type region which constitutes the base of the voltage setting transistor T is elongated relative to the base region of other transistors. A first electrical connection 45a is made to the base region adjacent the baseemitter junction and a second connection 45b is made at the end of the base region away from the emitter. This second connection also makes contact to the collector region of the transistor. The elongated P-type region between the connections 45a and 45b thus serves both as the resistance component R between the collector and base of transistor T and as the base region of the transistor. The magnitude of the resistance depends on the resistivity and dimensions of the region.

FIG. 6 is a schematic circuit diagram of the equivalent circuit of the combined transistor-resistor element of FIG. 5. Under normal operating conditions as explained previously the positive supply voltage V is applied at the connection 45b. The resistance R is thereby connected between the supply voltage and the base of the transistor, and there is a direct connection between the voltage source and the collector region.

When the logic circuit of FIG. 1 is functioning as explained previously in this application, the transistor T is caused to conduct by virtue of the termination of a signal at its base (via connection 45a) which increases the base potential while the output terminal of the circuit which is connected to the emitter is at a low voltage level. Heavy current flows through the collector and emitter to charge the load capacitance and to raise the voltage level at the output terminal. Since the only resistance connected between the output terminal and the voltage source is that of the heavily conducting transistor and the forward biased diode, the voltage at the output terminal is increased to the desired level in a very short time, on the order of 8X 10* seconds.

With an ordinary transistor connected to a resistance, voltage source, and output terminal in this manner, if the emitter should be held at a low potential as by inadvertent grounding of the output terminal, the transistor would tend to draw a heavy current. Although a transistor can safely pass a heavy current during the few nanoseconds required to charge the load capacitance, sustained current fiow may burn out an ordinary transistor subjected to this short circuit condition.

By virtue of the length of the current path from the connection 45b for the supply voltage at the collector or the transistor T to the emitter, however, a resistance eifect to sustained high current flow is produced in the element. This effect between the connection 45b and the collector junction of the transistor is indicated by a resistance 50 illustrated in phantom in FIG. 6. The short circuit current through the transistor is reduced by the resistance effect and burnout does not occur. The structure may also be thought of as causing a premature saturation effect in the transistor under conditions of sustained high current flow, thereby causing a drop in the amplification factor of the transistor and consequently limiting the collector current.

Logic circuits according to the invention provide many advantages over circuits previously available. The time required for the circuit to be completely turned on after a high voltage level is applied at each input terminal is small. Even more significant, the time required for restoring the voltage at the output terminal from the low level to the high level after the voltage level at an input terminal is reduced is very rapid. This propagation delay is usually the limiting factor determining the operating rate of known logic circuits.

The circuits disclosed are relatively immune to triggering by noise. The amplification provided by transistors in the circuit permits a large difference in the false and true voltage levels employed. Thus, spurious signals are much less likely to affect the circuit.

In each circuit the output terminal is restored to the high voltage level by current supplied from the voltage source through the elements of the circuit. That is, the restoring current for charging the load capacitance is not supplied from succeeding logic circuitry. The circuit is, therefore, relatively insensitive to loading and the fan-out (number of succeeding circuits which can be connected to the output terminal) is large. Isolation of each circuit from the adjacent circuits eliminates any tendency for components in one circuit to deprive a component in an adjacent circuit of current necessary for proper operation. Because of the current gain in the circuit and the load capacitance driving capability of the voltage setting transistor, a high input impedance is allowable at the input terminals; and, therefore, high fanout can be obtained without requiring heavy power dissipation in the circuit.

What is claimed is:

1. A circuit element comprising;

a body of semiconductor material having a first region of one conductivity type, a second region of the opposite conductivity type contiguous said first region and forming a PN junction therewith, and a third region of the one conductivity type contiguous said second region and forming a PN junction therewith,

a first electrical contact to said third region,

a second electrical contact to said second region adjacent the junction between said second and third regions, and third electrical contact to said first and second re gions spaced from said second electrical contact whereby said second region provides resistance between the second and third electrical contacts, the distance between said third electrical contact and the junction between the second and third regions being greater than the distance between said second electrical contact and junction between the second and third regions.

A transistor circuit element comprising;

body of semiconductor material having a collector region of one conductivity type formed at one surface of the body, an elongated base region of the opposite conductivity type diffused into a portion of the collector region from the one surface and surrounded by the collector region except at the one surface, the base region forming a PN junction with the collector region, and an emitter region of the one conductivity type diffused into a portion of the base region from the one surface and surrounded by the base region except at the one surface, said emitter region being located at one end of the base region and forming a PN junction with the base region,

first electrical contact to the one surface of the body of semiconductor material at the emitter region, second electrical contact to the one surface of the body of semiconductor material at the one end of the base region adjacent the emitter region, and third electrical contact to the one surface of the body of semiconductor material at the base and collector regions at the end of the base region removed from the emitter region, the distance between said third electrical contact and the junction between the emitter and base regions being greater than the distance between said second electrical contact and the junction between the emitter and base regions, whereby said first electrical contact serves as a terminal to the transistor emitter, the second electrica 1 1 1 2 contact serves as a terminal to the transistor base, 3,124,703 3/ 1964 Sylvan 307-885 the third electrical contact serves as a terminal to 3,138,744 6/1964 'Kilby 317 l0l the transistor collector, and the portion of the el n- 3,173,069 3/1965 Stehney 317 235 gated base region between the second and third elec- 3 229 119 1/ 19 h et 1, 307 88 5 trical contacts serves as a resistance between the 5 3,237,062 2/1966 Murphy 317 23 collector and base terminals of the transistor. 3,250,968 5/1966 Jochems at all 317 235 UNITED STATES PATENTS 3,263,138 7/1966 Nowalk et al. 317-235 References Cited JOHN W. HUCKERT, Primary Examiner. 2,985,804 5/1961 Buie 317-235 R. F. SANDLER, Assistant Examiner.

3,070,762 12/1962 EVHIIS 33370 

